Thought Leaders

Why the AI Chip Race Now Runs on Software

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Every new AI accelerator arrives with a benchmarking story: peak throughput, teraops per watt, impressive numbers that promise this chip will change everything. What those numbers leave out is whether the customer can actually use the chip in production. Most often, they can’t, and that’s the real story of where the AI hardware industry stands today. It faces a software maturity problem, and most companies aren’t yet ready to say so publicly.

The Gap Nobody Talks About

Silicon development cycles run two to four years, while the AI model landscape evolves on a cycle measuring months and trending towards weeks. Underlying this sits a value chain problem: end-use cases, from vehicles and factories to hospitals and devices, are maturing in functionality and beginning to generate measurable P&L impact. That maturity drives demand for software adaptations, which in turn require hardware changes. Each of these three layers operates at a fundamentally different speed, and that misalignment is the root cause of the friction building across the market. The software stack required to run large language model inference differs fundamentally from what was built for earlier machine learning workloads. Hardware development timelines have not compressed to match this cycle. Companies shipping new silicon today hand it to customers with software that cannot fully unlock the chip’s capabilities, producing a pattern that repeats across the market: impressive silicon, immature software, slow adoption, and missed revenue. The chip does what it was designed to do. The issue is that customers cannot easily use it.

Consider what happened to the automotive industry. Cars themselves were largely a solved problem by the mid-twentieth century, but when software became the differentiator, companies with the deepest manufacturing legacies struggled most to adapt. Ford and GM knew how to build engines, but had no muscle memory for building operating systems. The AI hardware industry is living through the same transition now, and the parallel is uncomfortably precise. NVIDIA plays the role of the software-native disruptor, while traditional semiconductor companies are still figuring out how to sell developer ecosystems alongside silicon.

NVIDIA’s dominance has almost nothing to do with having the best chips. CUDA (Compute Unified Device Architecture) is twenty years old, with all the accumulated technical debt that implies, but what NVIDIA actually built is the operating system of AI compute: a predictable, mature ecosystem that developers and OEMs can rely on in production.

Customers select platforms based on software maturity and integration risk, so when a new accelerator arrives without a production-grade software stack, the commercial conversation ends before it starts.

Time to first model, defined as how quickly a customer gets a real AI workload running on a given accelerator, is a far more meaningful commercial metric than peak throughput. That’s the conversation most hardware companies are least prepared to have.

The Real Market is Inference

The native language of business is the P&L, and every company deploying AI needs to answer the same question: where is the money, and what’s stopping me from capturing it? Training is a necessary step, but commercial AI lives in inference, and that market has barely started.

The scale asymmetry here is striking. Training covers one use case; inference covers an infinite number. Every application of AI in a vehicle, factory, hospital, phone, or warehouse requires inference. A chip running safety systems in a car can’t draw data center power, and a device running real-time inference on a factory floor can’t tolerate high latency. The edge inference market requires silicon designed specifically for power efficiency, physical constraints, and the safety and reliability requirements of the industries deploying it.

Google’s recent decision to split its eighth-generation TPU into two distinct chips, one for training and one for inference, is worth sitting with. This architectural choice acknowledges that the two workloads have diverged so significantly that optimizing for both in a single design now means excelling at neither. When a company running some of the largest AI infrastructure decides that specialization matters more than consolidation, it signals where the rest of the market is heading: toward purpose-built inference silicon deployed at the edge, in volume, under real-world constraints that data center benchmarks were never designed to measure.

We’re in an inference land grab, while most of the market remains organized around training.

The Structural Limits of Legacy

The companies best positioned to manufacture at scale remain structurally unable to serve the markets where inference will live. Automotive customers need suppliers to guarantee component availability for a decade. General-purpose semiconductor companies like Intel simply won’t commit to that. This structural constraint leaves an entire industry underserved, and no amount of negotiation changes it.

NVIDIA’s edge AI platform is already facing a challenge from PIN-compatible alternatives that deliver better performance per watt without requiring any changes to the software stack. A customer can swap the chip and keep everything else, making this a direct commercial attack on the most defensible part of NVIDIA’s edge position.

The companies that proved their concept on CUDA are discovering that economical deployment at scale demands re-architecture onto lower-power silicon, because when organizations roll out tens of thousands of devices, cost per unit and power consumption become decisive factors. The sequence playing out across the inference market is straightforward: use something that works, test it, then find a way to deploy it economically, because you need to make money on it. Given the pace of AI adoption, the window for establishing software and ecosystem advantage is measured in quarters.

The Engineering Investment Most Companies Are Skipping

AI hardware companies keep shipping powerful chips with software that can’t fully run them. Production-grade system software, covering inference runtimes, compiler optimization, and workload enablement, requires deep, specialized engineering that most hardware companies simply don’t have in-house.

Building that capability means hiring the compiler engineers and runtime architects who can close the gap between what a chip is theoretically capable of and what a customer can practically deploy. Companies also need to invest in toolchains before the revenue justifies it, because by the time the revenue arrives, the window has closed. Companies that skip that investment don’t just fall behind. They lose deals.

The chips that achieve scale are the most deployable chips, and deployability is a function of software quality. Major downstream buyers, from OEMs and hyperscalers to enterprise customers, have been burned before by silicon that benchmarks well and integrates badly. They choose based on ecosystem maturity and integration risk. Companies that treat software as a first-class engineering priority convert more pilots into production contracts and reach revenue faster. Those that treat it as a shipping afterthought watch technically superior silicon lose deals to inferior chips backed by more mature stacks.

The Clock Is Already Ticking

The AI hardware companies positioned to capture significant share in the next phase are building ecosystem advantages today that will be difficult for later entrants to replicate. Software flexibility, the ability to adapt to new model architectures without waiting for the next tape-out, separates silicon that stays commercially relevant from silicon that cycles endlessly through pilots without ever generating the revenue needed to fund the next generation.

The decisions being made right now, in engineering teams, partnership agreements, and commercial pilots across the AI hardware landscape, will determine which companies are still relevant in 2028. CUDA’s twenty-year head start is a moat built on ecosystem depth, but any company willing to treat software as a sustained engineering priority can build that same depth over time.

The question the industry needs to answer is which companies are moving fast enough to build the ecosystem depth that makes their chips the default choice before someone else’s becomes too entrenched to displace.

Craig Melrose is the Global Managing Partner for Advanced Technologies at HTEC, where he helps clients apply AI and digital engineering to complex business and industrial challenges. He brings more than 20 years of experience in operations and digital transformation, including senior leadership roles at PTC and McKinsey & Company, and earlier experience improving Toyota’s production performance in North America