MemryX Announces MX3+ to Expand Low-Power Edge AI Inference

MemryX AI announced the MX3+ inference accelerator on November 10, 2026, setting design targets of up to 10 times more peak AI compute and nearly 10 times more on-chip memory than MX3 while remaining within the same low-power operating envelope.

The fabless semiconductor company is aiming the device at edge hardware, industrial systems and high-density inference infrastructure running larger or more complex models. Its MX3+ product page adds that the design is intended to retain MX3’s silicon footprint and provide 10 times more model-weight capacity, addressing board-space and system-cost constraints as well as power.

Planned workloads include higher-resolution vision, transformer-based models, small language models, vision-language-action models, hybrid architectures and more sophisticated multi-model pipelines. Target deployments span industrial automation, robotics, intelligent transportation, smart infrastructure, video management, healthcare devices, retail and consumer electronics.

Design Targets and the Current MX3

Those figures describe a future product. The current MX3 is available for volume orders, and MemryX lists it at 6.25 TFLOPS of AI compute and 10.5 MB of on-chip weight memory per chip, with power consumption spanning 200 mW to 3 W.

The comparison establishes the central constraint for MX3+: increase compute and model storage substantially without expanding the power or physical budget that shaped its predecessor. The announced figures remain design targets until MemryX produces and validates the new hardware.

Multi-Chip Scaling as One Logical Device

Planned configurations will scale from one MX3+ to 16 chips operating as a unified logical device. MemryX says the 16-chip configuration is designed to deliver more than 1 POPS, meaning one peta-operation per second, of peak AI compute and 2.16 GB of distributed on-chip memory.

Distributed dataflow allows the accelerators to work together without requiring the host processor to manage individual chips. The MemryX Neural Compiler automatically maps neural networks across the available accelerators, letting developers scale performance without manually partitioning their models.

MX3+ combines the additional on-chip memory with near-memory, pipelined processing that keeps model data close to computation, minimizing data movement. The design targets larger models and higher-resolution inputs while maintaining predictable, low-latency inference at batch size one.

The existing MX3 datasheet documents the same scaling ceiling: host offload over PCIe or USB, support for x86, Arm and RISC-V processors, and PCIe cascading of up to 16 chips through a single host interface. MX3+ retains that multi-chip approach and a familiar development workflow as models and systems become more complex.

President and CEO Ross Jatou said MemryX expects the shared architecture to provide one development-to-production path across embedded, industrial and high-density systems and to significantly lower total cost of ownership for high-density edge deployments.

Early Access Before Volume Production

MemryX is accepting early-access requests from selected strategic partners and enterprise customers to co-validate pre-production hardware and software. It is targeting engineering samples for late 2027 and volume production for mid-2028, with further specifications, configurations and availability information to come as development progresses.

MemryX says new capabilities in MX3+ will carry into MX4, its future platform for advanced multimodal and large-language-model inference.

The official MX4 product page adds advanced vision and generative AI to its target workloads and targets availability in 2029.

The immediate work is validation rather than deployment. Early-access systems will need to show that the compute and memory gains can coexist with MX3’s power and footprint constraints while preserving compiler-led scaling and predictable low-latency inference.