Expedera Demonstrates Edge AI Subsystem Pairing with Cadence

Expedera announced on November 9, 2026, that it had paired its Origin Evolution neural processing unit (NPU) IP with Cadence’s Tensilica NeuroEdge 130 AI Co-Processor in a pre-silicon simulation, demonstrating how the two semiconductor IP blocks divide and execute AI inference workloads.

Expedera described the result as a validated pre-silicon integration, not a customer-silicon benchmark. The combined subsystem is designed to improve performance and power efficiency while reducing latency, cost and complexity, but the announcement supplies no combined measurements for those goals. The companies are targeting inference designs across edge nodes, smartphones, automotive systems and data centers, and the approach can be extended to other Tensilica digital signal processors.

Sharad Chole, Expedera’s chief scientist, said models are running on the combined subsystem and agentic AI workflows are helping the company deliver customized IP more quickly, giving customers “a faster, lower-risk path to production edge AI tailored to their performance and power requirements.”

How the Co-Processor and NPU Divide the Work

Amol Borkar, group director of product management and marketing for Cadence’s Tensilica Products Group, said the co-processor assists Expedera’s NPU with pre-processing, post-processing and operator fallback while also executing AI networks. The arrangement creates a division of labor inside the subsystem rather than assigning identical tasks to two accelerators.

Cadence designed the co-processor to work alongside its Neo NPUs, customer-developed NPUs or third-party NPU IP, making the Expedera pairing a concrete example of the third-party route. Its product documentation describes an Xtensa-based architecture using very long instruction word (VLIW) and single instruction, multiple data (SIMD) techniques, with optimized instructions for operations including sigmoid, tanh and ReLU that are less suited to NPUs.

The NeuroEdge 130 can also issue instructions and commands to an NPU as a control processor, adding programmability for workloads not anticipated when the subsystem was designed. It connects through AXI or Cadence’s High Bandwidth Direct Interface. The NeuroWeave software development kit, built on the Tensor Virtual Machine stack, is used to tune, optimize and deploy models on Cadence AI IP.

Origin Evolution breaks neural networks into packets, or contiguous fragments, and routes them through Feed Forward, Attention and Vector processing blocks. The blocks handle varying operations, data types and precisions; the NPU also supports LLMs, CNNs, RNNs and custom or black-box layers. This packet design is intended to reduce large memory movements while allowing different kinds of network work to share one architecture.

Earlier Launches Clarify the New Integration

Origin Evolution debuted on May 20, 2025 as available, production-ready and silicon-proven in customer production designs. Its launch figures apply to the NPU alone: Expedera reports scalability to 128 TFLOPS in one core and petaFLOPS and beyond with multiple cores, plus a reduction of more than 75% in external memory moves for Llama 3.2 1B and Qwen2 1.5B compared with alternative solutions.

Cadence had likewise introduced NeuroEdge 130 on May 7, 2025, with general availability and ISO 26262-ready status for automotive applications. Cadence reported more than 30% area savings and over 20% lower dynamic power and energy at comparable performance to Tensilica Vision DSPs on AI networks and operators. Those figures compare the co-processor with Cadence’s Vision DSPs; they do not measure the new Expedera-Cadence subsystem.

For edge SoC designers, the development is a validated integration path between two existing IP families: Expedera’s packet-based acceleration and Cadence’s programmable handling of surrounding operators and unforeseen workloads. It addresses a practical design tension in edge inference—specialized acceleration for dense network math versus enough programmability to accommodate changing models—within a subsystem that can be configured for different performance and power targets.