Hans Hasselby-Andersen, CEO of Lotus Microsystems – Interview Series

Hans Hasselby-Andersen is CEO of Lotus Microsystems, with more than 20 years of experience across the semiconductor industry as a founder, executive, board member, and investor. He founded Merus Audio and led it through its acquisition by Infineon in 2018, and has held leadership positions at Texas Instruments, Infineon, Toccata Technology, and Nokia. His work has centered on bringing energy-efficient semiconductor technologies to market.

Lotus Microsystems is a Copenhagen-based fabless semiconductor company developing integrated power converters and power delivery solutions for advanced electronics. Its silicon Power Interposer Technology combines power conversion with thermal management, including through its vStrata vertical power delivery platform for AI and high-performance computing. In this interview, Hasselby-Andersen discusses server-level energy losses, the limits of conventional power architectures, and why power delivery, cooling, and semiconductor packaging increasingly need to be designed together.

Your career has spanned wireless systems at Nokia, semiconductor development at Texas Instruments, founding Merus Audio and taking it through an acquisition by Infineon, and now leading Lotus Microsystems. How has that experience shaped the way you think about the power and thermal challenges emerging in today’s AI infrastructure?

I got into semiconductors almost by accident. A startup I was working with was acquired by Texas Instruments, and that became my introduction to how chips are designed, manufactured, and brought to market. I wasn’t a chip designer myself, but I learned a tremendous amount about the industry.

Later, when I founded Merus Audio, the catalyst was spotting a clear market gap, which was the need to reduce power losses and extend battery life in wireless speakers. From there, I focused on securing the right people and technology to address it.

After Merus was acquired by Infineon, I spent some time outside the semiconductor industry, but ultimately realized it was where I wanted to be. What drew me to Lotus Microsystems was the founding team’s focus on three fundamentals of its advanced power delivery technology: energy efficiency, physical size, and thermal performance. Those are challenges that never really go away in power delivery, regardless of the application, but AI has made them particularly urgent.

We’re seeing extraordinary progress in processor technology, but all that computing power comes with very real physical constraints. My experience has taught me that solving those less visible problems can be just as valuable as developing the technology everyone is paying attention to.

AI infrastructure discussions tend to focus heavily on GPU performance, networking, and cooling. Why do you believe power delivery itself is becoming one of the most important constraints on the continued scaling of AI systems?

We spend a lot of time talking about how much computing power a GPU can deliver, but much less about how to get enough electricity to it efficiently. Modern AI accelerators require thousands of amps of current at very low voltages, and their power demands can change almost instantly depending on the workload. Traditional power delivery systems weren’t designed for that level of intensity. You can have the most advanced processor in the world, but if you can’t deliver stable power when it’s needed, you’re not going to get its full potential. That’s why power delivery is becoming such an important part of the AI scaling challenge.

When data center operators talk about energy efficiency, much of the attention is placed on cooling systems and facility-level metrics. How much power is actually being lost inside the server before it reaches the processor, and why has this issue received comparatively little attention?

There’s no single number that applies to every server, but the losses can be substantial. In certain high-current architectures, we’ve estimated that roughly 7–10% of power can be lost in the final stages of delivery to the processor. That energy isn’t doing any useful computing; it’s being converted into heat, which then needs to be removed. When you’re operating thousands of processors around the clock, even relatively small inefficiencies become very expensive.

One reason this has been overlooked is how we’ve traditionally measured data center efficiency. Power Usage Effectiveness, or PUE, has become the industry standard, and it’s useful for understanding facility overhead, including cooling and power distribution. But it doesn’t show how efficiently electricity is being converted and delivered inside the server itself.

I’m not suggesting cooling efficiency isn’t important; it absolutely is. But there’s something a little backwards about spending enormous amounts of money removing heat without paying enough attention to where some of that unnecessary heat is coming from. We should be trying to prevent those losses in the first place.

As GPUs and other AI accelerators consume increasingly large amounts of power, what limitations are emerging in traditional board-level power delivery architectures?

The problem becomes clearer when you look at how power actually reaches a GPU. In a traditional design, the power converters sit alongside the processor, and electricity travels horizontally through the circuit board to reach it. That distance might seem insignificant, but when you’re moving thousands of amps, even small amounts of resistance matters. Resistive losses increase with the square of the current, meaning doubling the current through the same resistance can quadruple those losses.

There’s also the challenge of responding to rapid changes in power demand while maintaining stable voltage. Engineers can compensate by adding capacitors, and other components, but those approaches take up valuable space. Eventually, it makes more sense to rethink the architecture than to keep adding to the existing design.

What changes need to happen in the way power is delivered from the server rack to the processor if the industry wants to continue increasing compute density without creating unsustainable thermal or efficiency problems?

There’s already a lot of innovation happening at the rack level, including the move toward higher-voltage power distribution. That’s important because higher voltages allow electricity to be transmitted with less current, reducing losses over longer distances. But eventually, that electricity still needs to be converted down to the very low voltages that processors require, and that’s where some of the most difficult challenges remain.

One of the most promising developments is vertical power delivery, which brings power conversion directly beneath the processor rather than placing it beside it. Shortening that electrical path helps reduce losses and improve response times. But it also introduces a challenge of its own, which is that you’re bringing heat-generating components much closer together. To make these architectures work at scale, we need to stop treating power delivery, thermal management, and packaging as separate engineering exercises. They have to be designed together from the beginning.

Lotus Microsystems recently introduced its vStrata vertical power delivery platform. What problem is vertical power delivery intended to solve, and how does this approach differ from conventional power architectures used in AI servers today?

The basic idea behind vertical power delivery is relatively straightforward. Instead of moving enormous amounts of current horizontally across a circuit board, you bring the power source directly beneath the processor. This dramatically shortens the electrical path, reducing losses and helping the system respond more quickly when power requirements change.

But there’s an important distinction between moving power closer to the processor and actually solving the entire problem. You’re also concentrating heat in a smaller space, right next to components that are already operating under significant thermal pressure. If you don’t address that, you risk creating a new bottleneck while solving the original one.

That’s what we set out to address with vStrata. Our proprietary silicon Power Interposer Technology allows us to deliver power vertically while incorporating thermal management into the same architecture. Our first module, the LSC0580, is engineered for up to 96% point-of-load efficiency, with temperature reductions of up to 25°C in optimized configurations. The goal isn’t simply to move more current, but to help data centers get more useful compute from the same physical footprint while reducing the power and cooling overhead needed to support it.

The AI industry often assumes that future performance gains will come from better chips or more advanced semiconductor processes. Could improvements in power architecture ultimately be just as important to AI performance as advances in the processors themselves?

Absolutely. A processor’s theoretical performance is only useful if the surrounding system allows it to operate at that level. If power delivery can’t keep up with demand, or excessive heat forces the system to throttle performance, you’re not getting everything you paid for. What’s interesting is that better power architecture can help unlock more sustained performance from existing hardware without necessarily changing the processor itself. I wouldn’t frame it as a choice between better chips and better infrastructure. We need both, and I expect the relationship between them to become increasingly important.

AI data centers are already placing significant pressure on electricity grids around the world. How much could improvements in server-level power conversion and delivery reduce the overall energy footprint of large-scale AI infrastructure?

The potential is substantial, although it’s difficult to put one figure on it because the impact depends on the architecture and scale of the facility. A percentage point of improvement in one conversion stage doesn’t automatically translate into the same reduction in total data center electricity consumption.

But consider what happens when you multiply even modest efficiency improvements across thousands of processors running continuously. You’re potentially talking about significant reductions in wasted energy, operating costs, capital expenditure, and the amount of heat that cooling systems need to manage. That’s particularly valuable when grid capacity is already limiting where and how quickly new data centers can be built.

Another way to put it is that the greenest energy is the energy you never use. There’s been tremendous focus on securing more power to support AI expansion, which is understandable, but we should be equally interested in making better use of the electricity that’s already available.

As AI hardware moves toward higher-power GPUs, custom accelerators, and increasingly dense computing systems, what technical bottlenecks do you expect power engineers to encounter over the next several years?

Current requirements are going to continue increasing, and we’re already seeing the challenges that creates. Some AI processors require several thousand amps, with future designs potentially reaching 6,000 or even 8,000 amps. Delivering that current efficiently is difficult enough, but keeping voltage stable as workloads change rapidly adds another layer of complexity.

The industry also tends to focus on current density as the main measure of progress. It’s impressive to deliver more current from a smaller power converter, but if you’re generating the same amount of heat in a smaller space, you haven’t necessarily made the overall system better. In fact, you may have made the thermal problem worse. I think the engineers who can balance efficiency, thermal performance, dynamic response, and reliability will be the ones who make the biggest advances.

Looking toward the next generation of AI infrastructure, what changes across power delivery, cooling, semiconductor packaging, and system architecture will be necessary to support another major increase in AI compute capacity?

I expect we’ll see much tighter integration between power delivery and the processor itself. Vertical power delivery is an important step, but I don’t think the evolution stops there. We’re already looking toward thinner power modules that can be embedded into circuit boards, and eventually architectures where more of the power delivery functionality is integrated directly into xPU packages. Each step brings power closer to where it’s actually consumed.

Cooling will have to evolve alongside those changes. Liquid cooling is becoming increasingly important for high-density computing, but improving how we remove heat is only part of the equation. We also need to reduce how much unnecessary heat we generate and find better ways to manage it close to the source.

Perhaps the biggest change will be how these systems are developed. Traditionally, different parts of the hardware stack have often been optimized somewhat independently. At the power levels we’re moving toward, that becomes increasingly difficult. Chipmakers, power electronics specialists, packaging engineers, and system designers will need to work much more closely together. We’ve spent years pushing the limits of individual processors, but the next phase of AI infrastructure will be about making sure the entire system can support what those processors are capable of.

Thank you for the great interview, readers who wish to explore vertical power delivery and thermal management for AI infrastructure should visit Lotus Microsystems.