Efficient Computer Raises $97M+ Series B at $650M Valuation to Scale Processors

Efficient Computer announced on September 29, 2026 that it entered into agreements for more than $97 million in Series B financing at a $650 million valuation, led by TQ Ventures. The company said it will use the capital to ship its Electron E1 processor in volume to lead customers and to scale its Fabric architecture to datacenter-class performance.

Financing Terms and Investors

The round brings Efficient Computer’s total funding raised to $173 million, according to the announcement, which describes the company as building the world’s most energy-efficient processors. Participants alongside TQ Ventures include Eclipse, Union Square Ventures, Giant Ventures, Triatomic Capital, TO Capital, TF Capital, Mana Ventures, Toyota Ventures, Overmatch, and Borderless. Efficient said the scaling effort is aimed at datacenter-class performance with a more than 10x improvement in energy consumption over systems built today.

In a companion blog post published the same day, CEO and co-founder Brandon Lucia restated the $97 million Series B, the $173 million total raise, and the $650 million valuation. Lucia wrote that he, Nathan, and Graham founded Efficient Computer about 10 years earlier to fundamentally rethink computer architecture, solving for efficiency without compromising generality.

The company’s Series B page identifies the leadership team as Lucia, chief executive officer; Graham Gobieski, chief technology officer; and Nathan Beckmann, chief architect.

Fabric Architecture and the Electron E1

Efficient describes its Fabric architecture as a clean-slate redesign of computing and claims a 10-100x improvement in energy consumption for general-purpose computation, including AI. The company contrasts that general-purpose approach with what it calls specialized “AI-only chip” alternatives, which it says do not support most software and risk instant obsolescence as AI evolves.

According to the announcement, the architecture supports the most popular software frameworks through a frontend that handles C, C++, and many other common abstractions. The Series B page adds that developers can use C, C++, LiteRT, and ONNX to run AI alongside sensing, control, and application code on one programmable processor, and can recompile and update devices already in the field as models change.

On its homepage, Efficient claims the Electron E1 is up to 100x more efficient measured on whole applications running on real silicon, rather than idle power or a single kernel hand-tuned for fixed-function hardware. The page describes the effcc Compiler as a drop-in replacement for GCC or Clang that extracts parallelism, places and routes a program onto the Fabric, and compiles in minutes.

Efficient said the Electron E1 is in volume production and that customers are adopting it for physical AI and autonomy, critical infrastructure observability, space and defense, and wearable devices. Application spotlights on the homepage describe the E1 running a drone’s entire autonomy pipeline on one part, bringing real-time processing and predictive maintenance to remote infrastructure sensors, and processing more data on board spacecraft so that only mission-critical findings are downlinked in standard C and C++.

The announcement also states that the Fabric can replace power-hungry embedded GPUs in a robot autonomy stack, enabling the system to operate at 10 times less energy, and that at the high end of the performance range it accelerates varied and irregular datacenter workloads that are a poor fit for AI accelerator chips and GPUs.

“Every customer we meet has a version of their product they cannot build, because the compute power budget makes the new capabilities they want infeasible,” Lucia said in the announcement. He said the round extends that effort to many more use cases and domains as Efficient scales the Fabric architecture from devices already shipping toward datacenter scale.

Founding History and Technical Rationale

In his blog post, Lucia argued that with CMOS process scaling slowing alongside the end of Moore’s Law and Dennard Scaling, most compute performance gains have come from architectural tradeoffs that prioritize performance at a cost in efficiency, including massive power-hungry memory structures, interconnects, and front-ends that attempt to extract parallelism from sequential instruction streams. He invoked Amdahl’s Law against fixed-function accelerators: in his example, even if 90 percent of a computation fits an accelerator and that portion’s time and energy cost dropped to zero, the maximum benefit would be 10x because the remaining 10 percent stays inefficient.

Lucia wrote that Efficient’s technology brings a 10-100x energy-efficiency improvement compared to traditional CPU architectures, and that the company has already begun work to scale it to domains with higher performance requirements: humanoid autonomy, self-driving, and agentic AI at the edge and in the cloud.

Investor Statements and Next Steps

Andrew Marks, co-founding partner at TQ Ventures, said Efficient’s architecture differs fundamentally from existing designs and brings what he called a step function in efficiency to general-purpose computing, adding that the founders’ ability to build both the hardware and the software convinced the firm. “Not only have they taped out four times, but they’re already shipping chips to customers at volume,” Marks said.

Rebecca Kaden, general partner at USV, said the company’s ability to deliver such gains across the performance spectrum will change how computing is built and deployed, from physical AI to the data center. Zenetta Burger, USA lead partner at Giant Ventures, said the founders spent years at Carnegie Mellon working through the architectural problems behind energy-efficient computing. Greg Reichow, a partner at Eclipse, said the firm backed Efficient from the very beginning and that the same architecture is scaling from physical AI to the datacenter with customer demand accelerating.

Statements from additional backers appear on the company’s Series B page. Chris Abshire, a partner at Toyota Ventures, said pairing accelerator-class efficiency with general-purpose programmability enables more capable systems in settings where power has long limited what can be built. Patrick O’Kain, a partner at Borderless Capital, said power is the true constraint on where serious computing capacity can sit, across commercial and national security uses, and noted that the E1 is already shipping in volume.

Efficient said it has scaled Electron E1 production to meet what it described as overwhelming customer interest and will continue scaling volume into 2027 to serve its global customer base. The Series B page frames the round as taking the company’s technology from its first processor to a broader range of products, with chips in development for applications that run on embedded GPUs and the Fabric architecture extended toward datacenter-scale computing.