Synopsys and TSMC Expand AI Design Work to A14 and Co-Packaged Optics

Synopsys on September 23, 2026 announced a new set of collaborations with TSMC aimed at accelerating the development of next-generation AI, high-performance computing (HPC), and advanced semiconductor systems, spanning certified design flows on TSMC’s A14 process, agentic AI engineering workflows, multi-die packaging support, co-packaged optics, and expanded 2nm silicon IP.

The companies said the joint work combines AI-powered electronic design automation (EDA) flows, multiphysics-aware signoff methodologies, multi-die design flows, and silicon-proven Interface and Foundation IP, and is intended to help mutual customers address growing design complexity while accelerating adoption of TSMC’s latest process and advanced packaging technologies.

“As AI systems continue to grow in scale and complexity, customers require proven IP, intelligent design solutions, and advanced packaging methodologies that work together seamlessly,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “Our joint innovations with TSMC address the continuum of silicon to systems co-design capabilities needed to accelerate development of next-generation AI and high-performance computing systems.”

Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC, said the collaboration under TSMC’s Open Innovation Platform (OIP) pairs certified EDA solutions and silicon-proven IP from Synopsys with TSMC’s latest process and packaging innovations, and said the work addresses customer demands around performance, integration, and energy efficiency in AI and high-performance computing.

A14 Certification and Agentic AI Workflows

Among the recent achievements the companies cited is A14 certification across Synopsys’s digital and analog flows, along with enablement of agentic AI capabilities. Synopsys said the certified flows provide customers with a comprehensive methodology spanning implementation through signoff to accelerate design convergence on TSMC’s A14 technology.

In analog design, the two companies are collaborating on device routing enablement on A14, which the announcement describes as a key milestone for advanced analog place-and-route automation that boosts layout productivity and speeds adoption of advanced process technologies.

The companies are also applying agentic AI to automate analog, digital, and multi-die design workflows for greater productivity and autonomy. According to Synopsys, its Custom Compiler tool accelerates analog migration, while Fusion Compiler uses large language model-assisted analysis to boost productivity.

For faster heterogeneous integration in multi-die designs, Synopsys said a new agentic AI chiplet floorplan co-optimization flow using its 3DIC Compiler platform automates complex floorplanning tasks and accelerates design convergence while supporting TSMC’s 3DFabric technologies.

Multi-Die Power Delivery and Co-Packaged Optics

The announcement describes integrated voltage regulators (IVRs) as a key technology for improving power efficiency and power integrity in multi-die designs as next-generation AI systems drive power delivery requirements. Synopsys said its 3DIC Compiler platform now enables designers to co-design and simulate IVRs on TSMC’s CoWoS technology within a unified environment for advanced packaging.

Synopsys also said it is continuing joint enablement work with TSMC for co-packaged optics (CPO) design on TSMC-COUPE technology through an integrated photonic and electronic co-design flow spanning 3DIC implementation, multiphysics analysis, and optimization. Both companies said the effort helps mutual customers develop and verify advanced optical interconnect architectures for systems using multi-die designs.

Silicon IP Milestones on N2P and N3P

Synopsys said it provides Interface, Foundation, and Silicon Lifecycle Management (SLM) IP optimized for TSMC’s advanced process technologies, building on first-silicon success across TSMC’s N5, N3P, and N2P technologies. The company described the portfolio as the industry’s broadest of its kind and said it is aimed at helping customers reduce risk, accelerate time-to-market, and achieve power, performance, and scalability goals across AI, HPC, data center, edge, and physical AI systems.

On TSMC’s N2P process, Synopsys reported IP enablement and tape-out milestones for AI and HPC designs covering PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and advanced SLM process, voltage, and temperature (PVT) monitoring IP. The company said these solutions deliver the high-bandwidth connectivity, memory performance, and real-time system intelligence needed for demanding AI workloads.

For multi-die integration, Synopsys said it demonstrated UCIe-A 32G/40G silicon on a TSMC N3P test chip integrated with a CoWoS-S interposer, validating high-speed die-to-die connectivity for AI systems. The company also recently completed 64G UCIe IP tape-outs on both 2nm and 3nm process nodes, and said the IP provides in-system visibility through embedded design-for-test capabilities.

Synopsys said it recently expanded its portfolio of silicon-proven Foundation, MIPI, and memory IP for TSMC’s N3P and N2P processes and is developing IP on compact “C” process technologies from 6nm through 3nm. According to the company, those IP solutions enable higher integration, lower power consumption, and faster deployment across AI, data center, networking, mobile, automotive, and edge AI applications.