Synopsys Certifies Its Chip Design Tools on Intel’s 14A Node

Synopsys has certified its chip design software for Intel (INTC ) 14A, the process node Intel has said it will fund only against confirmed customer commitments. The company announced the certification on July 27, 2026 at the Design Automation Conference in Long Beach, California, covering its digital and analog implementation and signoff flows, multiphysics analysis for power, heat and electromagnetic behaviour, and a set of interface and foundation IP blocks tuned to the node.

That is the toolchain a customer needs in place before it can commit to a node, which is what makes the state of Intel 14A’s design ecosystem worth more attention than a routine tool announcement. Nvidia (NVDA ) used the same conference to put its own CPU to work designing its next chips.

What a certified flow buys

A leading-edge process is unusable to an outside chip designer until the software that turns a chip description into manufacturable layout has been tuned to that process and validated against its design rules. Certification is the foundry’s sign-off that a vendor’s toolchain clears that bar. Before it exists, a prospective customer cannot start real work on the node.

Synopsys said the certified flows pull multiphysics analysis into implementation rather than leaving it to signoff. At 14A geometries, with power delivered from the back of the wafer and dies stacked in three dimensions, thermal, electrical and mechanical effects stop behaving as separable problems. Synopsys frames the payoff as fewer late-stage reworks and better odds of first-pass silicon. Pulling simulation earlier into engineering tooling has been a running theme at this year’s show, where Nvidia also wired physics simulation into its AI agent toolkit.

The company also extended 3DIC Compiler, its multi-die design environment, to Intel’s EMIB and EMIB-T packaging, the silicon bridges Intel uses to stitch separate dies together inside a single package. The flow covers bump and through-silicon-via planning, automated routing for UCIe die-to-die links and high-bandwidth memory stacks, and power-delivery and thermal analysis across the whole assembly. In a March 2026 engineering post, Synopsys put the scale of the problem at packages reaching 120 mm by 180 mm and substrates carrying more than 30 bridges.

On the IP side, Synopsys listed new blocks aimed at AI and high-performance parts: 224G SerDes, PCIe 7.0, USB 4 and eUSB interfaces, plus foundation IP covering embedded memories, logic libraries and I/O cells. Those are the pieces a customer licenses rather than designs itself, and having them ready shortens the distance between picking a node and taping out on it.

Why Intel gated 14A on customers

Intel’s position on this node has been unusually blunt. In a July 2025 letter to employees, chief executive Lip-Bu Tan said Intel was developing 14A as a foundry process built from the ground up around large external customers, and that spending on it would follow confirmed commitments: “There are no more blank checks.”

The second-quarter 2026 results, reported July 23, 2026, show why the discipline matters. Intel Foundry booked $5.8 billion in revenue, up 31% year over year, against a $2.09 billion operating loss. Intel reported $5.5 billion of intersegment eliminations for the quarter, the line that strips out sales made between its own business units, and it did not break out external foundry revenue. The release’s own risk language names the open question directly, citing the company’s efforts to secure design wins and demand commitments from potential significant external customers for 14A and later nodes.

The certification also marks how far the tooling has travelled. At Intel Foundry’s Direct Connect event in April 2025, Intel said it had distributed an early 14A process design kit to lead customers and that several intended to build test chips on it. Synopsys, in its announcement that same day, described its 14A work as early co-optimization on a preliminary variant while its Intel 18A flows were already certified. Fifteen months on, 14A has certified flows and a named IP list.

What comes next for 14A

Intel has said the node will use PowerDirect, a direct-contact power delivery scheme succeeding the backside power network in 18A. Intel’s nearer-term manufacturing work sits with 18A-P, which entered risk production in June 2026.

Ecosystem tie-ups are the currency foundries trade in ahead of design wins. GlobalFoundries and SEALSQ announced one of their own (LAES ) around post-quantum security in July 2026.

For designers evaluating Intel Foundry, the practical change is that 14A now has a validated route from design entry through signoff and advanced packaging, with licensable IP attached. For Intel, certified tools clear one of the obstacles between a prospective customer and the kind of commitment its capital plan for the node depends on.