Nvidia Puts Its Own CPU to Work Designing Its Next Chips

Nvidia (NVDA ) has begun running the chip-design software its own engineers use to build the company’s next generation of processors on its Vera CPU, and Cadence and Synopsys are tuning their tools to match.

The company said Cadence Jasper, a formal verification platform, and Synopsys VCS, the logic simulator used to validate designs before fabrication, each showed up to 1.5 times higher performance on selected workloads in initial testing. Nvidia said the VCS test held the core count constant, which makes the reported gain a per-core one rather than the result of adding hardware.

The disclosure came alongside a broader engineering announcement at the Design Automation Conference in Long Beach, California, where Nvidia also detailed agentic tooling built with Cadence, Siemens and Synopsys, whose contribution was a fully autonomous verification agent. Nvidia is running the deployment on a Vera cluster in its Portland data center, according to a photo caption in the post.

The workloads acceleration can’t reach

The post carries a notable admission from a company that sells accelerators. Nvidia’s own framing is that acceleration has limits here. GPUs and AI have taken over large parts of chip design, it says, but logic simulation, formal verification and stretches of digital implementation are still gated by the CPU, by how fast one core runs and how quickly memory can feed it.

That is the commercially interesting part. Verification and regression clusters are among the largest general-purpose CPU fleets a chip company operates, and they sit directly in front of tapeout, the point in a project where schedule slips cost the most. They are also a class of work that does not move to GPUs, which makes them one of the few remaining places in a chip company’s data center where the CPU vendor choice is the entire decision. The installed base is substantial: Synopsys describes VCS as the primary verification solution at a majority of the world’s top semiconductor companies.

Vera is Nvidia’s Arm-based data-center processor, built around 88 custom Olympus cores, an LPDDR5X memory subsystem and a second-generation coherency fabric that links cores, cache and I/O across a single compute die. Nvidia designed the part for agentic AI, where the CPU executes tool calls and code between model steps. Chip verification turns out to want the same properties: fast individual cores, kept fed, running thousands of jobs at once.

What the 1.5x number leaves out

Nvidia does not say what the 1.5x is measured against. The post names no comparison processor, no design under test, no software versions and no absolute runtimes. The claim is “up to 1.5x higher performance on selected workloads,” and selected is carrying weight in that sentence.

Nvidia has been more precise about Vera elsewhere. Its product page baselines the chip’s headline figure, up to 1.8x on agentic sandbox work, against what it calls the latest-generation x86 CPU. A company post published July 7, 2026 put Vera at 1.8 times the sustained per-core performance of x86 under load and described a Perplexity test on a real coding workflow. The chip-design figures carry no equivalent framing.

Independent numbers on Vera are thin, and the ones that exist were gathered under conditions Nvidia set. Michael Larabel published what he described as some of the first public benchmarks of the chip in a Phoronix review on May 26, 2026, run across a single day at Nvidia’s Santa Clara offices. He wrote that Nvidia restricted the tests to workloads it considered relevant to Vera’s target customers and asked that CPU power and frequency monitoring stay switched off while power management was still being tuned. No EDA tools appeared in the published set.

Designing the next chip on the last one

The strategic shape of this is a loop. Nvidia is using its own CPU to design the CPUs and GPUs that come after it, then feeding what it learns back into the silicon. The company said it plans to build on Vera with a next-generation processor called Rosa, powered by a core named Rigel. Its earlier post described Rigel as an Arm v9.2 design delivering higher per-core performance than Olympus within the same silicon footprint, with better instruction delivery, a larger L2 cache and more efficient memory handling. Core counts, clock speeds and dates remain undisclosed.

For verification managers at other chip companies, the decisive number is not 1.5x. It is whether Cadence and Synopsys ship production-supported, qualified Arm builds of Jasper and VCS. Moving a regression farm to a different instruction set means requalifying a flow that has to be trusted all the way through tapeout, and tool vendors, not benchmark charts, set that timeline. Nvidia describes application profiling, software optimization and system-level tuning as continuing work, and gives no availability date for the optimized builds.

Vera itself is still ramping. The same Phoronix review reported the chip on track to ship in the second half of 2026, and Nvidia’s Blackwell-generation systems are what is landing in customer data centers today. What the chip-design deployment signals is the ambition Nvidia has for Vera beyond its role hosting GPUs in Rubin racks: a general-purpose data-center CPU whose first reference customer is Nvidia’s own silicon team.