Synopsys Hands Chip Verification to Autonomous AI Agents

Synopsys said on July 26, 2026 that it has built a design verification agent capable of running a chip’s entire verification cycle without an engineer driving it, and that the system reaches validated RTL up to 50 times faster while delivering a further 20% improvement in coverage. The company announced the work at the Design Automation Conference in Long Beach, California, where it is demonstrating the flow for the first time. Nothing ships yet. Customers are evaluating the capabilities now, with availability planned for the second half of 2026, a window that has already begun.

The agent combines Synopsys AgentEngineer technology with NVIDIA’s (NVDA ) agentic stack: the NVIDIA Agent Toolkit, the Nemotron 3 Ultra open model, and a sandboxing layer NVIDIA calls the OpenShell runtime. An orchestrator agent pulls verification goals from the specification, the design, the existing test repository and engineer input, then dispatches specialized agents across test-plan generation, coverage closure and debug. Coverage closure is the step where a team proves its tests actually exercised the logic, and Synopsys describes it as one of the biggest bottlenecks in the process.

The speedup numbers are the vendors’ own

Every performance figure here comes from the companies selling the tools, and the baselines are thin. The 50x and 20% claims carry a footnote comparing them to “traditional verification workflows not powered by AgentEngineer technology,” with no named design, no process node and no engineer-hours attached. The analog claim, up to 3x productivity for a mixed-signal flow orchestrated by the same technology, rests on a footnote that essentially restates itself.

Four months earlier, at its own Converge conference on March 11, 2026, Synopsys described a less autonomous version of the same idea, an “L4” multi-agent design and verification workflow, and put the gains at 2x productivity with up to 5x in selected cases. That release also noted that front-end design of a large system-on-chip typically occupies a verification team for four to six months. The two metrics are not identical, but the distance between 2x in March and 50x in July is wide enough to want a customer’s own before-and-after figures before treating it as settled.

There is no help from independent testing. Training and inference silicon has MLPerf, a common submission format with a public results table; agentic design flows have no benchmark of record at all. NVIDIA’s adjacent claim, that Nemotron 3 Ultra leads open models on agentic register-transfer-level coding, rests on a benchmark NVIDIA publishes, measured using an agent NVIDIA Research built. Startups chasing the same market, among them Chipmind, which launched from stealth to rebuild chip design around AI agents, face the same evidence gap.

Where the EDA workload actually runs

The second half of the announcement is less about agents than about hardware. Synopsys says more than 20 of its EDA and multiphysics products are now GPU-accelerated. It reports circuit simulation in PrimeSim SPICE running roughly 18 times faster in overall wall-clock time on NVIDIA GPUs than on CPU-only runs, a 10x speedup for Ansys Lumerical electromagnetic simulation, and up to 50x for quantum-chemistry work in QuantumATK using NVIDIA’s cuEST library.

That is a substantial block of engineering compute moving off CPU racks and onto NVIDIA hardware inside the design houses that build accelerators. NVIDIA’s own announcement adds a sparse-solver library, cuISS, to its CUDA-X set and says the Synopsys VCS simulator is being tuned for its Vera CPU. The tools that design the next generation of AI silicon increasingly run on the current one.

Synopsys also showed an autonomous workflow for electronics thermal analysis, built on Ansys Icepak, the cooling simulation tool it picked up in the Ansys acquisition, plus the open-source PyAEDT libraries. It handles simulation setup and pre- and post-processing unattended. NVIDIA’s description of the same work names the application more plainly: GPU cooling design optimization. Tim Costa, NVIDIA’s vice president and general manager for computational engineering, said the agents help teams “close verification, automate thermal analysis and compress development cycles from weeks to hours.”

Every EDA vendor picked the same partner

NVIDIA’s release lists Cadence, Siemens, Samsung, Keysight, Silvaco and TSMC alongside Synopsys. Cadence’s packaging and board flow is credited with up to 20x faster multiphysics performance. Siemens says agentic workflows cut library characterization time by more than 10x while reducing token costs by a similar factor. Samsung reports up to 20x on computational lithography using cuLitho. All three major EDA vendors anchored their autonomy stories to the same supplier’s models, libraries and runtime on the same day.

Two things would make the claims checkable. The first is a customer publishing coverage-closure numbers from a named design at a named node. The second is clarity on whether the second-half availability window means general release or limited early access.

The deployment question has the most at stake. Nemotron is an open-weight model that can be post-trained on proprietary data and run locally, a point NVIDIA makes explicitly. RTL is among the most closely guarded intellectual property a chip company holds, valuable enough that governments have weighed restricting its export. An autonomous verification agent needs the whole design to do its job. Whether it can do that job inside the customer’s own firewall decides who can use it at all.