Siemens Makes Its Chip Design AI Agents Check Their Own Work

Siemens opened the Design Automation Conference with a pitch about trust rather than raw speed: its chip design agents will now check their own work against the tools that decide whether a design passes. The company announced on July 26, 2026 an expanded partnership with NVIDIA (NVDA ) that turns its Fuse EDA AI Agent system into what Siemens calls a self-verifying workflow, in which long-running agents validate each decision against deterministic, physics-based design engines instead of trusting the model’s own output.

That framing goes straight at the reason chip teams have been slow to hand real work to language models. An agent that writes register-transfer level code or clears a design-rule violation can be confidently wrong, and in silicon a confident error surfaces at tapeout, after the mask costs are sunk. Siemens’ answer is to keep the agent inside a loop closed by its own signoff tools, which return pass-or-fail answers that owe nothing to a model’s judgment.

The underlying machinery comes from NVIDIA. Siemens said it is building the agents with NVIDIA’s NeMo Gym library for agentic environments, running them inside the OpenShell secure runtime with role-based access controls and audit trails, and using the latest Nemotron models with NVIDIA’s Switchyard for reasoning. The agent system now also sits inside Intelligence Center X, the enterprise AI environment Siemens uses to connect design, manufacturing and supply chain.

What the agents actually touch

Coverage runs the length of the flow: high-level synthesis in Catapult, digital verification in Questa One and the Veloce emulation system, custom IC work in Solido, physical implementation in Aprisa, signoff in Calibre and design-for-test in Tessent, plus 3D IC integration in Innovator3D IC and board layout in Xpedition. Siemens launched the Fuse agent in March 2026 at NVIDIA’s developer conference, and this announcement extends that system rather than replacing it.

Two products carry the concrete news. The Solido Characterization Suite gains agentic workflows that generate and verify the timing libraries standard-cell, memory and custom IP teams work from. A new tool, Solido Layout Analyzer, applies natural-language prompting to parasitic and layout-dependent effects in post-layout designs, returning analysis, fix recommendations and reports.

The speedups have no referee

Siemens says the characterization workflow cuts turnaround times by more than 10 times and reduces token costs by five to ten times. NVIDIA’s own announcement of the same collaboration puts the token-cost reduction at more than 10 times, so the two first-party accounts of a single number already disagree. Neither release names the design, the process node, or the engineer-hours the comparison is drawn against.

On verification, which Siemens says consumes as much as 70 percent of design effort, the company is pairing the Questa One agentic toolkit it introduced in February 2026 with NVIDIA’s Nemotron 3 Ultra, and says the model leads among open models in agentic RTL benchmarking. That result comes from ACE-RTL, an agent built by NVIDIA Research, measured on a Verilog problem set NVIDIA itself publishes: a vendor scoring a vendor model on its own test.

The one named customer in the release has not run the software in production. STMicroelectronics’ non-volatile memory design manager, Gianbattista Lo Giudice, said the layout tool should cut weeks off the time his team spends debugging complex blocks, then added that the group is “planning to test and validate the advantages in our on-going design activity.”

None of it is checkable from outside. Agentic design flows have no MLPerf equivalent and no independent body publishing comparable results across vendors, so the claims Siemens, Synopsys and Cadence carried into Long Beach this week sit in a category where the marketing numbers are the only numbers.

What Siemens has actually committed

Availability is the softest part of the release. The expanded capabilities will arrive in “forthcoming releases” of the company’s EDA portfolio, with no date attached. Synopsys at least put a second-half-2026 window on its rival autonomous verification agent, and Cadence tied its claim of up to 20 times faster multiphysics work to a named hardware platform.

The documented commitment is capital. In the week before the conference Siemens agreed to buy two more EDA companies:

• Precision Innovations, announced July 20, 2026, a San Diego firm building AI-driven chip planning on the open-source OpenROAD framework, with closing expected in the third quarter of 2026.
• Defacto Technologies, announced July 21, 2026, a Grenoble developer of automated system-on-chip assembly founded in 2003.

Terms were not disclosed for either.

That is the pattern worth watching. The agentic layer is where the big EDA vendors are competing on speedups nobody can audit, and where venture-funded startups are pitching the same premise. The purchases underneath it are less glamorous and far more legible: Siemens is buying the design-creation and planning tools its agents will need something to call. Those tools are documented. The 10x is not.